KiPI Solver Guide

What power integrity analysis is, why it is worth doing before a board is built, and how KiPI's DC, thermal and AC solvers turn a PCB layout into voltages, currents, temperatures and impedances.

This page explains the ideas. The user guide explains every button, the setup and the results, and the README how to install KiPI.

What power integrity is

Every chip on a board needs its supply voltage held within a tolerance, typically a few percent, whatever current it draws. A voltage regulator (VRM) sets that voltage, but the chip does not sit at the regulator's pins: between them is the power distribution network (PDN), made of traces, planes, vias, the capacitors around the chip and the copper that carries the current back to ground.

That copper is not a perfect conductor. It has resistance, so a steady current drops voltage along the way, and it has inductance, so a current that changes quickly drops voltage too. Power integrity (PI) analysis predicts those drops and checks that what arrives at each chip is still in tolerance:

DC: the steady drop from resistance, V = I·R, and the heat the current makes in the copper.
AC: the drop from a changing current, set by the PDN's impedance across frequency, ΔV = Z(f)·ΔI.

The whole budget is shared: a 1.0 V rail with ±3% tolerance has 30 mV to spend, split between the regulator's own accuracy, the DC drop and the AC ripple and droop.

Why it matters

Supply voltages have fallen while currents have risen. A processor core at 0.8 V and 40 A has a total tolerance of about 25 mV. At that current, a single milliohm of copper uses 40 mV, more than the whole budget. A rail that is out of tolerance rarely fails cleanly. Instead it causes intermittent resets, bit errors, jitter on clocks and serial links, and failures that come and go with temperature or workload. These faults are hard to find on the bench and expensive to fix with a respin.

The layout decides most of the PDN, through plane shapes, neck-downs, via counts and where the capacitors go. PI simulation looks at it before fabrication, while fixing a problem means moving copper rather than adding bodge wires.

What KiPI simulates

Analysis	Answers	Results
DC voltage drop	Does every load get enough voltage at its full current? Which copper and vias carry the most current?	Voltage, current density and power density on every layer in 3D, current in every via, the voltage at every load pin, copper losses, and PASS/FAIL per load, VRM and via.
Electro-thermal (optional, with DC)	How hot does the copper get, and how much does that raise its resistance and the drop?	Board temperature map, the hottest copper per layer, and the DC results at that temperature.
AC PDN impedance	How stiff is the supply seen by a chip, from kHz to hundreds of MHz? Does it meet the chip's target impedance?	\|Z\|, R and X at each probe over frequency, against flat or custom targets, with each capacitor model's own curve.

All three use the same model of the board: the copper of each net on each layer, read from KiCad (or a board file), the stackup's thicknesses and materials, and a power tree you describe once. The power tree says which pads are VRM outputs, which are loads and what they draw, and which parts (sense resistors, ferrite beads, load switches) join one net to another.

The triangle mesh

Copper shapes on a real board are irregular: planes with antipads, traces that bend, thermal reliefs, pads of every shape. No formula gives the resistance of such a shape, so KiPI cuts it into many small triangles, works out how current flows across each one, and combines them. This is the finite element method (FEM).

A mesh made by Triangle, as KiPI makes them: quality triangles that shrink toward the drill hole and the pad. KiPI's default mesh is finer than this.

KiPI meshes each net on each copper layer with Jonathan Shewchuk's Triangle, a quality Delaunay mesher:

Quality. No triangle has an angle under 28° (Mesh tab, Min angle), since long thin triangles give poor answers. No edge is longer than Max edge (0.5 mm by default), so large planes still get enough triangles to show how current spreads.
Grading. Current crowds around vias and pads, so triangles shrink toward every drill hole, down to Min edge (0.02 mm), and grow again away from it. Detail is spent where the voltage changes fastest.
Pads and holes. Each load or VRM pad outline is built into the mesh, so the pad has nodes of its own to inject or draw current. Drill holes are holes in the copper, and the nodes around each rim are where the plated barrel joins that layer.
2.5D. Each layer is a flat sheet with the copper's thickness. Vias and plated holes join the sheets of different layers through their barrels. Current flowing through the thickness of a single sheet is not modeled, which suits board copper, which is tens of microns thick and millimeters wide.

The number of nodes (unknowns) sets the solve time, from thousands on a small board to millions on a large one with fine meshing. A coarser Max edge solves faster; a finer one resolves narrow necks and small planes better.

DC: voltage drop

At DC, current in a copper sheet flows from high to low voltage, spreading out wherever the copper is wider. The voltage V on the sheet obeys

∇·(G_s ∇V) = 0, with sheet conductance G_s = t / ρ

where t is the copper thickness and ρ its resistivity (1.72×10⁻⁸ Ω·m for copper at 20 °C). 1 oz copper (35 µm) has a sheet resistance of about 0.5 mΩ per square: any square of it, of any size, measures 0.5 mΩ edge to edge. A trace 0.2 mm wide and 20 mm long is 100 squares, or about 50 mΩ.

On each triangle the voltage is taken to vary linearly. That turns the equation into a small conductance matrix per triangle, like three resistors joining its corners. Adding them up gives one large sparse system G·V = I: the conductance matrix, the unknown node voltages, and the currents injected at the pads. Then:

A via or plated hole joins the rim nodes on each layer it passes through, through its barrel's resistance ρ·L / (π(d·t_p − t_p²)) for drill d and plating t_p. A 0.3 mm via through 1.6 mm of board is about 1.3 mΩ.
A VRM output holds its pads at its set voltage (a fixed node voltage).
A load draws its current from its pads, shared equally between them or split into groups of pads with different current requirements.
A series part (a sense resistor, load switch or a ferrite bead's DC resistance) joins the pads on both sides through its resistance, so the nets it joins are solved as one.

Solving gives the voltage at every node. The current density comes from the voltage gradient, the via currents from the barrels, and the power lost in the copper from I²R summed over every triangle and barrel.

The power tree

Boards have more than one rail, and rails feed each other: a 12 V input feeds a buck to 3.3 V, which feeds an LDO to 1.8 V. KiPI solves them downstream first:

An LDO draws from its input what it delivers plus its quiescent current.
A switching regulator draws V_out·I_out / (η·V_in). Its input voltage depends on the drop on the input rail, which depends on the current it draws, so KiPI iterates the two until they agree.
Remote sense moves a VRM's output until its sense pins sit at the set voltage, as the real control loop does. This creates voltage boost in some places, and drop in other places.
Ground is a net like any other: loads return their current through their ground pins, so ground drops count too.

Tolerance analysis

Each load can have a tolerance: how far its supply may sit from the nominal voltage, as ± percent or in volts, taken from the load's datasheet. After the solve, KiPI checks every supply pin of the load. The worst pin's deviation from the VRM's set voltage (from DC drop on the rail, rise on ground, and a VRM load line if it has one) must be within the tolerance for the load to PASS. Any pin outside it makes the load FAIL, and the result tables show which pin and by how much.

Tolerance analysis answers "does this layout leave the chip enough margin?" rather than "what is the voltage?". Two points matter when choosing the number:

The datasheet tolerance covers everything, including the regulator's set-point accuracy and the AC ripple and droop. The DC drop may only use part of it. If a 1.0 V ±5% rail's regulator is ±1% accurate and you budget 2% for AC, the DC drop gets the remaining 2%: enter 2 for the load, not 5.
The regulator tolerance, the ±1% in the above bullet, can be derived from feeedback resistor tolerances and the regulator's datasheet specifications for its reference voltage accuracy.
Use the worst-case current, not the typical one, since drop scales with current. With electro-thermal on, the check uses the copper at its solved temperature, which is when its resistance is highest.

VRMs are checked too: whether the input left after the input rail's drop is still above the regulator's dropout and within its input range. A VRM that cannot hold its output fails every load downstream of it.

Electro-thermal co-simulation

The power lost in the copper, I²R, turns into heat. On a high-current rail that heat raises the board temperature by tens of degrees, and the heat from neighboring planes, regulators and loads adds to it. KiPI's thermal model spreads that heat across the whole board:

∇·(G_th ∇T) − 2h (T − T_amb) + q″ = 0

G_th is how well the board spreads heat sideways: every copper layer (weighted by how much of each spot is copper, on any net) plus every dielectric layer's in-plane conductivity, from its material in the stackup.
h is the convection from each face to the air, about 10 W/m²K in still air (with radiation) and rising with the airflow you set.
q″ is the heat per area: copper and via losses, series parts, VRM conversion losses and, optionally, the loads' own power.

Through its thickness the board is taken as one temperature at each point. For FR4, the resistance across 1.6 mm is about a tenth of the resistance from the surface into the air, so the layers sit within a degree or two of each other.

Hot copper resists more

Copper's resistivity rises with temperature, by about 0.393% per °C near room temperature:

R(T) = R₂₀ · (1 + α (T − 20 °C)), α ≈ 0.00393 /°C

Copper that runs 50 °C hotter than 20 °C has about 20% more resistance, and at 100 °C about 31% more. The physics behind it: as the copper heats, its atoms vibrate harder and scatter the electrons carrying the current more often.

That forms a loop: current heats the copper, the heat raises its resistance, more resistance means more drop and more I²R loss, and that loss heats it further. KiPI's co-simulation follows the loop:

Solve the DC power tree at the current temperature map (20 °C everywhere at first).
Gather every loss on the board onto one grid, and solve the board temperature.
Set each triangle's resistivity from the temperature where it sits, and go back to step 1.

Each pass reports how much the peak temperature changed. On most boards it settles within a few passes, which is when DC drop and temperature agree. A rail that keeps heating from pass to pass is a warning in itself: its copper is too narrow for its current.

The temperature coefficient can be set per layer in the Stackup window, for conductors other than copper.

AC: PDN impedance

What PDN impedance is

Chips draw current in bursts: a processor that wakes up, an FPGA's clock that starts, an amplifier at full swing. The regulator's control loop corrects slowly, typically within tens or hundreds of kHz, so faster changes in current are supplied by the capacitors and the planes. How much the voltage moves for a given change in current depends on frequency:

ΔV(f) = Z(f) · ΔI(f)

PDN impedance Z(f) is the impedance a chip sees looking out of its power pins into the power supply network. It is the ratio of voltage change to current change, and it depends on every capacitor, plane and via between them and ground. It is a complex number at each frequency: KiPI shows its magnitude |Z| and its resistive and reactive parts.

A typical PDN curve. Each group of capacitors pulls the impedance down near its resonance. Where one group hands over to the next, an inductance meets a capacitance and the impedance peaks (an anti-resonance). Above the plane's range, inductance wins.

A real capacitor is not a pure capacitance. It also has an equivalent series inductance (ESL, from its construction, termination, and mounting) and resistance (ESR). These factors vary greatly from capaitor to capacitor and case size to case size. Below its self-resonant frequency it acts as a capacitor and its impedance falls with frequency. Above it, it acts as an inductor and its impedance rises. That is why a PDN uses many values: bulk capacitors for low frequencies, many small ceramics for the middle, and the plane pair's own capacitance for the top. Where one hands over to the next, the curve has peaks (anti-resonances), and those peaks are where a rail is most likely to fail.

Target impedance

If the voltage may move by ΔV while the load steps by ΔI, the PDN must stay below the target impedance

Z_target = ΔV / ΔI

up to the highest frequency in the step. A 1.0 V rail allowed 3% (30 mV) of transient for a 10 A step needs Z_target = 3 mΩ. A step that rises in time t_r has most of its energy below f ≈ 1 / (π·t_r), which is how far the target applies. KiPI's target calculator works both out from the load's transient spec (after Smith et al., 1999). Some chip vendors publish a frequency-dependent target mask instead, which KiPI takes as corner points.

KiPI leaves the regulator out of the AC model and computes the open-loop PDN impedance. Below the regulator's control-loop bandwidth, the loop is assumed to hold the voltage. Above it, the loop is too slow, which is the range a target applies to, so you give each VRM's bandwidth and the targets are judged from there up. Other analysis methods can model the interaction with the control loop and the capacitive portion of hte PDN, this is called closed-loop analysis and is outside the scope of KiPI.

How KiPI models it

The AC solver uses the same triangle mesh, extended for the fields between rail and ground copper:

Two faces per sheet. At high frequency, current crowds onto the copper surfaces (the skin effect: about 6.6 µm deep at 100 MHz) and onto the face looking at the return current. Each copper sheet therefore has a top and a bottom face, joined at its edges, holes and pads, and the copper's internal impedance moves from its DC resistance to surface resistance with frequency.
Inductance. A face looking at ground copper a distance h away has a loop inductance of μ₀h per square, 126 pH per square for 0.1 mm of dielectric. Thin dielectrics between power and ground keep the inductance low.
Capacitance. Facing rail and ground copper is a capacitor of ε₀ε_r·area / h, with the dielectric's loss tangent. 100 cm² of 0.1 mm FR4 is about 3.8 nF, a small capacitor of very low inductance that matters at hundreds of MHz.
Vias join the faces of each layer through their barrels. Their inductance, and the inductance of a capacitor's mounting, comes out of how current spreads to them on the planes. You enter only each capacitor's own self ESL, not its mounting.
Capacitors are series RLC models at their pads. A ferrite bead or resistor between nets is a series link and can include DCR and ESL.

For two facing planes this is the classic plane-pair (cavity) model, so plane resonances come out of the mesh, as does the spreading inductance between a capacitor and the chip. The sweep factorizes the copper model at a few frequencies per decade, solves for every capacitor and probe port at once, interpolates that smoothly, and adds the capacitors at each of the many frequencies plotted. This keeps a sweep from 1 kHz to 300 MHz at a few hundred points per decade fast. Note this this creates a massive computational problem. AC solves can take a long time.

Effective vs nominal capacitance

The capacitance printed on a ceramic capacitor (MLCC) is measured at 1 kHz, 25 °C, with no DC voltage, when the part is new. On a board it is often much less. KiPI uses the capacitance you enter for each model, so enter the effective value at your rail's conditions. Four effects stack up:

Effect	What happens	Typical size
Dielectric	Class I dielectrics (C0G/NP0) are stable. Class II (X7R, X5R, X6S) use barium titanate, whose very high permittivity depends on temperature, voltage and time. The code gives the temperature range and the allowed change across it. Class III (Y5V, Z5U) varies far more.	C0G: ±30 ppm/°C. X7R and X5R: ±15% over their range. Y5V: +22% / −82%.
DC bias	A DC voltage across a class II dielectric aligns its ferroelectric domains, which then respond less to the AC signal, so the permittivity falls. Small cases and low voltage ratings have thinner layers, a stronger field at the same voltage, and lose the most. C0G does not have this effect.	Often −30% to −80% at the rated voltage. A 10 µF 0402 6.3 V X5R part can keep under half its capacitance at 3.3 V. Good design practice dictates that a cap should only be exposed to half its rated voltage, for both safety factor purposes and to minimize DC bias impact.
Aging	After a class II part last cooled through its Curie point (about 125 °C, as in reflow), its domains slowly relax and its capacitance falls logarithmically with time: the same loss each decade of hours. Heating above the Curie point resets it ("de-aging").	X7R: about 1–2% per decade hour. X5R: about 3–5%. That is roughly 5–15% after a few years in the field.
Manufacturing tolerance	Parts are sold within a tolerance of the nominal value, coded by a letter (K = ±10%, M = ±20%).	−10% or −20% at the low end.

The effects multiply. A worst case for that 10 µF X5R part on a 3.3 V rail at 85 °C:

10 µF × 0.45 (DC bias) × 0.85 (temperature) × 0.92 (aging) × 0.80 (tolerance) ≈ 2.8 µF

More than two thirds of the capacitance is gone. Lower capacitance raises the impedance below the part's resonance and moves the resonance up, by the square root of the ratio, while the inductance above resonance does not change. Capacitor makers publish DC-bias and temperature curves per part, and their online tools (Murata SimSurfing, TDK SEAT, KEMET K-SIM, Samsung's tool) give the capacitance, ESR and ESL at a chosen bias and temperature. Enter the manufacturer's delectric, tolerance, aging and DC bias factors. KiPI can work out how each impacts the PDN impedance.

Linear solvers and PARDISO

Every analysis ends in a large sparse system of equations, one unknown per mesh node. DC and thermal systems are symmetric positive definite; AC systems are complex. How KiPI solves them:

Solver	How it works	Used for
SuperLU (SciPy)	A sparse direct solver: it factorizes the matrix once, then each right-hand side is a fast forward and back substitution. Single-threaded. Always installed.	Systems up to about 200k unknowns without PARDISO.
AMG-CG	Conjugate gradients, an iterative solver, preconditioned by algebraic multigrid (pyamg). Uses much less memory than a factorization, but has to iterate for every right-hand side.	DC and thermal systems above the direct limit.
PARDISO (Intel MKL)	A parallel sparse direct solver. It factorizes on every CPU core and handles complex systems too.	Up to 1M unknowns, if installed.

PARDISO is an optional install (the pypardiso package). Its benefits:

Speed on large boards. Factorizing is the slow step, and PARDISO uses every core. On a 645k-unknown rail one solve drops from about 8 s to 1.2 s, and a four-pass electro-thermal run from about 90 s to 34 s.
A higher direct-solve limit. With PARDISO, KiPI factorizes systems of up to 1M unknowns instead of 200k. A factorization is reused for every load, power-tree iteration and AC port, which an iterative solver cannot do, so fine meshes stay fast.
AC sweeps. Each field frequency of an AC sweep is a complex factorization, so large AC models gain the most.

The drawbacks: Intel MKL is about 600 MB installed, it exists only for x86-64 Windows and Linux (not macOS or ARM), and small boards, which solve in a second either way, gain little. That is why it is not installed by default. KiPI falls back to SuperLU on its own if PARDISO is missing, cannot load, or returns an inaccurate result, and the results are the same either way. Because PARDISO utilizes all cores, the machine running the simulation will really stretch its legs. Expect high CPU utilization and higher junction temperatures, at the gain of simulation speed. About → Copy version info says which solver is in use. See the README for how to add it.

What PI simulation finds

Design problems KiPI typically exposes, and where to look for each:

Problem	How it shows	Typical fix
Neck-downs	A bright spot in the current density where a plane narrows between holes, or a pour squeezes past a connector.	Widen the path, move the obstacle, add a parallel layer.
Too few vias	Vias over their current rating in the via table, or one via carrying most of the current while its neighbors idle.	Add vias, spread them along the current's path.
Load out of tolerance	A load FAILs; the voltage map shows where the drop is.	Thicker copper, a wider pour, the VRM closer, or remote sense at the load, or add more parallel copper planes.
Ground drop	The ground net's own voltage map, with load grounds sitting tens of mV above the VRM.	Solid ground under the current's path; no slots across it. More ground planes
Sense in the wrong place	The sense point meets its set voltage while the far loads fail.	Sense at the most critical (high current, tighter tolerance) load, or where the loads are grouped.
Hot spots	The temperature map, the hottest copper per layer, and a drop that grows with each electro-thermal pass.	More copper or layers, a wider path, airflow.
Anti-resonance peaks	\|Z\| above the target between two capacitor groups, or where the plane resonates.	Add intermediate values, change ESR, physically move capacitors in the layout.
Capacitors too far away	High impedance above a few MHz at the probe despite enough capacitance on the rail.	Move capacitors next to the pins, shorten their vias, use thinner dielectric to ground. Consider smaller case size/lower ESR/lower ESL capacitors at load. Adding these at supply will do little.

What KiPI does not model

DC: copper is solid and its thickness uniform. Plating variation and etch undercut are not modeled; KiPI uses the stackup's thicknesses.
Thermal: steady state only, with one temperature through the board's thickness and no heat carried away by the parts, enclosure or conduction into the mountin. No heatsinks; this tool is meant to model copper losses and expose weak points, not simulate the thermal scenario of an entire system.
AC: the regulator is left out (open-loop impedance). The package and die are not in the model; probes sit on the board's pads. Capacitors are fixed RLC models, so DC bias and aging are for you to apply to the value you enter. Radiation and coupling to signal nets are not modeled.

Like any simulation, the results are only as good as the setup. Check that the load currents are worst case, the capacitor values effective, and the stackup right. The tool is incredibly powerful with thoughtful and complete inputs.